The present and foregoing application claim priority to Japanese Application No. P2000-176216 filed Jun. 13, 2000. All of the foregoing applications are incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and in more detail a method for fabricating semiconductor devices in which a multi-layered wiring structure is formed by the dual-damascene process.
2. Description of the Related Art
Aluminum alloy has widely been used as a wiring material for LSIs. It has, however, been becoming more difficult to ensure sufficient properties (high reliability and low resistivity) with such aluminum alloy wiring in recent trends toward downsizing of LSIs and speeding-up in the operation thereof. One countermeasure for solving such problems relates to copper wiring which is more excellent in electromigration resistance and lower in resistivity as compared with those of conventional aluminum alloy wiring, and has been introduced into some of semiconductor devices.
In the copper wiring process, groove wiring is considered to be practical since copper is generally less processible by dry etching. In the groove wiring, a predetermined groove is formed in an insulating film typically made of silicon oxide, the groove is then filled with a wiring material, and then the excessive portion of such wiring material is removed by, for example, chemical mechanical polishing (abbreviated as CMP hereinafter), to thereby form a wiring within the groove.
Methods for filling a wiring material in the groove wiring process, which are under investigation, include electrolytic plating process, chemical vapor deposition process (abbreviated as CVD hereinafter), a combined process of sputtering and reflow, high pressure reflow process, and electroless plating process. Among these, electroless plating process is practiced in recent fabrication of semiconductor devices in view of film formation rate, film formation cost, purity of the obtained metal film and adhesiveness.
An exemplary process for filling, by the electroless plating process, copper as a wiring material into the groove and a connection hole will be described below.
A groove is formed in an intermediate-layer insulating film provided on the base member. On such intermediate-layer insulating film and on the inner surface of the groove, a barrier layer typically comprising a tantalum nitride (TaN) film of 30 nm thick is formed by sputtering. The barrier layer is responsible for preventing copper from diffusing into the intermediate-layer insulating film made of a silicon oxide film. Next, the plating seed layer typically comprising a copper film of 150 nm thick is formed by sputtering on the plating seed layer. The plating seed layer serves as a seed layer for assisting growth of a copper layer through the successive electrolytic plating.
Next, on the surface of such plating seed layer, a copper film is grown by electroplating so as to fill the groove and so as cover the intermediate-layer insulating film while being interposed with the barrier layer.
An excessive portion of the copper film on the intermediate-layer insulating film is then removed to thereby form a wiring. While the removal generally employs CMP, one possible alternative relates to a method in which the copper film formed by electroplating is subjected to etch-back by electrolytic polishing. The electrolytic polishing refers to a polishing method in which metal surface is dissolved on the anode side in a special solution to thereby obtain a smooth and glossy surface. It has been a conventional practice to employ the electrolytic polishing mainly for deburring and raising glossiness of the surface with respect to aluminum or stainless steel, and for pretreatment of plating with respect to copper or copper alloy.
For the case the electrolytic polishing process is adopted to the wafer process, it will be necessary to bring an electrode 111 in contact with a plating seed layer 103 which is previously formed on a wafer 101 while being interposed with a barrier layer 102 as shown in FIG. 3A. In some cases, it is also necessary to seal the outer peripheral portion of the wafer 101 using a seal member (e.g., O-ring) so as to avoid contact between the contacted electrode 111 and an electrolytic polishing fluid 121.
This, however, allows the plating seed layer 103 to be remained after completion of the electrolytic polishing in a portion not brought into contact with the electrolytic polishing fluid (not shown) such as those shadowed by the electrode 111 or on the outer peripheral portion of the wafer 101 as shown in FIG. 3B. Such residual plating seed layer 103 will be causative of a large height difference on the outer peripheral portion of the wafer 101.
Forming an insulating film 104 in the next process step will thus result in the formation of a large step portion S on the surface of such insulating film 104 due to the pattern edge of the residual seed layer 103 as shown in FIG. 3C. This requires an another process step for planarizing the surface of the insulating film 104. Failure in removing such step portion S will be causative of peeling off of a wiring formed further thereon.
As has been described in the above, residual metal wiring material in a field of a wafer will result in various disadvantages such as inter-wiring short-circuit and degraded step portion coverage.
It is therefore an object of the present invention to provide a method for producing semiconductor devices for the purpose of resolving the foregoing problems.
A first method for fabricating semiconductor devices according to one embodiment of the present invention comprises the steps of: forming a plating seed layer on the base member (e.g. wafer); forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.
The first method for fabricating semiconductor devices has the step for selectively removing the plating seed layer remaining on the outer peripheral portion of the base member, so that the plating seed layer will never remain on the surface of the base member after the electrolytic polishing in a portion where an electrode for use in such electrolytic polishing is brought into contact, which desirably reduces in-plane height difference of the base member. Such reduction in the in-plane height difference after the electrolytic polishing and such removal of an unnecessary portion of the plated film and the plating seed layer composing the wiring material films can successfully raise the yield ratio of semiconductor devices, and can beneficially exclude necessity for post-growth planarization by CMP of the insulating film to thereby reduce the production cost.
A second method for fabricating semiconductor devices according to another embodiment of the present invention comprises the steps of: forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; removing by etching the plating seed layer on the outer peripheral portion of the base member; and polishing the plated film together with the plating seed layer by the electrolytic polishing process.
The second method for fabricating semiconductor devices has the step for removing by etching the plating seed layer on the outer peripheral portion of the base member, so that the plating seed layer will never remain on the surface of the base member after the electrolytic polishing, which desirably reduces in-plane height difference of the base member. Such reduction in the in-plane height difference after the electrolytic polishing and such removal of unnecessary portions of the plated film and the plating seed layer composing the wiring material films can successfully raise the yield ratio of semiconductor devices, and can beneficially exclude necessity for post-growth planarization by CMP of the insulating film to thereby reduce the production cost.